1. Field of the Invention
The present invention relates to a semiconductor device having a decoupling capacitor which suppresses or compensates a momentary drop in direct current voltage occurring at the time of a load variation in an LSI device operating at a high speed.
2. Related Art
FIG. 24 of the accompanying drawings shows a variation (ΔV) in the DC voltage V supplied to an LSI device 104 in the case in which the LSI device 104, which performs high-speed switching with a rise time of t1, is mounted to a circuit board 111. In FIG. 24, there is no decoupling capacitor mounted, which suppresses or compensates for a voltage variation ΔV in the DC voltage supplied to the circuit board 111. The reference numeral 101 in FIG. 24 denotes a power supply line, 102 is a signal line, 103 is a ground line, 105 is a DC power supply, and 106 are vias and through holes. FIG. 25 is the equivalent circuit of FIG. 24. When the LSI device 104 is switched at a high speed, the wiring between the DC power supply 105 and the LSI device 104, or the parasitic inductance L (L1+L2+L3+L4+L5+L6) 108 existing in the vias or through holes 106 cause a variation in the DC voltage V supplied to the LSI device 104. When this occurs, the amount of variation ΔV (voltage drop) in the DC voltage is given by the equation (1).ΔV=R×Δi+L×di/dt  (1)
In the above, R is the resistance and L is the inductance of the wiring and the capacitor, and Δi is the current variation over the time Δt.
Therefore, the larger are the resistance R, the wire, the parasitic inductance L 108 existing in the via or through hole, or the load variation di, or the smaller is the variation time dt, the greater will be the increase in the voltage variation ΔV. In recent years, LSI device is driven at high frequency the clock rates of which having come to exceed several hundred megahertz. The rise time tr of a pulse waveform in a digital circuit is thus equivalent to the load variation time dt. The faster is the clock frequency, the shorter is the rise time tr, so that the greater is the amount of voltage variation ΔV. In addition to this effect, recent years have seen advancements in the reduction of the input voltage V in order to achieve LSI devices that operate at high speeds (for example, reduction from 3.3 V to 1.8 V), and there is a trend toward even greater increases in the voltage variation rate (ΔV/v), so that the value of ΔV/v exceeds the allowable value for an LSI device (approximately 5%). While no problem would arise if a switching power supply were to be able to compensate for this voltage variation, because a switching power supply requires from 100 ns to several μs of time in order to perform compensation, it cannot track the voltage variations encountered in an LSI device that is switched at a high speed (several hundred ps to 1 ns).
In order to prevent misoperation in a LSI device such as this caused by voltage variations, in the past a capacitor was connected in parallel between the power supply line and the ground line, this capacitor generally being referred to as a decoupling capacitor. A decoupling capacitor has two effects, the effect of bypassing a high-speed switching signal generated from the LSI device, shortening the path of a high-speed signal, and reducing the parasitic inductance (which will be referred to as the first effect hereinafter), and the effect of supplying the load from the decoupling capacitor (that is, discharging thereinto) so as to compensate for the voltage drop occurring temporarily when performing high-speed switching (which will be referred to as the second effect hereinafter). In accordance with Equation (1), in order to make ΔV small, the inductance L (in, for example, the wiring and the via and through holes) can be minimized, and recently in order to minimize this inductance, as shown in FIG. 26, a decoupling capacitor 109 is mounted directly to the side of the LSI device 104, or directly below the LSI device 104 via the intervening circuit board 111. FIG. 27 shows the equivalent circuit for this arrangement. By virtue of the first and second effects achieved by the decoupling capacitor, the amount of variation ΔV in the DC voltage supplied to the LSI device is reduced, as shown by the broken lines in the graph at the upper part of FIG. 27.
The main cause of an increase in the variation of the DC voltage supplied to an LSI device that switches at a high speed is parasitic inductance L existing in the wiring path between the LSI device and the decoupling capacitor. This parasitic inductance L is the parasitic inductance existing in wiring, a via hole, and a through hole. The parasitic inductance of the decoupling capacitor itself is yet another cause of voltage variation. In order to reduce the parasitic inductance of wiring, a via hole, and a through hole, it is necessary to make the lengths thereof be as small as possible. However, with a capacitor mounted in the vicinity of an LSI device, because there is a parasitic inductance of approximately 100 pH/mm in wiring, vias, and through holes, if we consider wiring lengths and the sizes of vias and through holes in the past, there would be a parasitic inductance of approximately 300 pH. Additionally, it is not possible to ignore the parasitic inductance of the decoupling capacitor itself (which, in the past, has been approximately 1 nH for each chip capacitor, so that if N capacitors are connected in parallel, the total effective parasitic inductance would be 1 nH/N). Because of the existence of these parasitic inductances, if we consider the case of a DC supply voltage of 1.8 V and high-speed switching equivalent to 500 MHz, the voltage variation rate ΔV/v would be at least approximately 10 to 15%, this representing the cause of misoperation of the LSI device.
Additionally, in the past the resonant frequency of a decoupling capacitor was low, this being in the range from several tens of MHz to 80 MHz, there was the problem that the decoupling capacitor failed to function effectively as a decoupling capacitor when the LSI device clock frequency reached over several hundred MHz, so that there was a need to make the resonant frequency of the decoupling capacitor itself higher (because a high-speed signal of a frequency higher than the resonant frequency of the decoupling capacitor resulted in a lag that prevented the proper tracking for load compensation, thereby making it impossible to effectively suppress voltage variation). In order to achieve a high resonant frequency in a capacitor, it is necessary to reduce the parasitic inductance of the decoupling capacitor itself, making it necessary to take measures with regard to such structural features as the shape of the capacitor electrodes and the electrolytic thickness and the like. According to Nikkei Electronics (Apr. 19th 1999 edition), pp. 144-156, it is known that reducing the electrolytic thickness reduces the parasitic inductance, and an invention related to a semiconductor device using a thin-film capacitor has been reported (for example, in Japanese unexamined patent publications (KOKAI) No. 11-458822 and 8-97360).
If we take the case of an LSI device (A) having a clock frequency fH of 100 MHz, a maximum current consumption I of 10 A, and a power supply voltage V of 3.3 V, and an LSI device (B) for which fH=500 MHz, I=90 A and V=1.8 V, if a calculation is performed of the capacitance C of a decoupling capacitor required to compensate for the voltage drop ΔV (assumed to be 10% of the rated voltage) during one clock cycle, because the electrical charge Q required to compensate for the voltage drop is Q=C×ΔV=I×(1/fH), from the relationship ofC=I/(fH×ΔV)  (2)
the required capacitance C in the case of the LSI device (A) would be 10 A/(100×106×3.3×0.1)=0.30 μF, while in the case of the LSI device (B), the required capacitance C would be 90 A/(500×106×1.8×0.1)=1.0 μF. Thus, if the LSI device clock speed increases and also the power consumption becomes large, the capacitance required for the decoupling capacitor becomes larger.
For a given decoupling capacitor parasitic inductance, however, if the capacitance increases the LC resonant frequency (f=1/(2·δ LC) is reduced, there arises the problem that it is not possible to sufficiently supply the load within the time that the voltage drop occurs (that is, within the time between the rise and fall of the clock). This being the case, with the increasing speeds of LSI devices, it has become necessary to reduce the parasitic inductances of decoupling capacitor themselves. For example, in the case of a clock signal at 500 MHz, with a capacitor having a capacitance of 1.0 μF, if the resonant frequency is to be pushed higher than 500 MHz, it is necessary that the parasitic inductance be reduced to below 0.1 pH. Because this is not possible with a single capacitor, in practice this is done, for example, by connecting in parallel 100 low-capacitance/low-inductance decoupling capacitors, each having a capacitance C of 10 nF or less and an inductance (L) of 10 pH or less, between the power supply and ground. Because any reduction in the parasitic inductance of the decoupling capacitor results in a higher LC resonant frequency, to make up for the accompanying individual reduction in capacitance, it is necessary to mount a large number of capacitors in parallel. If 100 or more capacitors are mounted, mounting space for the capacitors and the associated wiring is required, thereby hindering the achievement of a small circuit board.
Accordingly, in order to solve the problems of the drawbacks in the conventional technology, as noted above, it is an object of the present invention to provide a semiconductor device having a decoupling capacitor that suppresses or compensates for a momentary drop in the DC voltage supplied to an LSI device operating at a high speed. It is a further object of the present invention to reduce the variation in the DC voltage supplied to the LSI device while reducing the size of the circuit board.